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Visiting Industrial Fellows
     
 
Sujay Desai, Ph.D. 2018

Electrical Engineering
Advisor: Prof. Javey
Research Interests: device physics, device engineering, sensors, memories, flexible and conformal electronics, quantum computing, neuromorphic computing
Job Interests: Industry R&D, post-doc

BIOGRAPHY
I am a dynamic and innovative experimental researcher with extensive experience in semiconductor fabrication, characterization and simulation. My expertise is in device physics and engineering, and exploration of materials and investigation of their properties. I have achieved demonstrable results in diverse areas ranging from: investigation of 1-nm gate length transistors, strain engineering, device modeling, to circuit design, with a focus on practical and industrial applications.

2D Semiconductor Transistors with 1-Nanometer Gate Length [BPN862]
MoS2 transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode are demonstrated. These devices exhibit near ideal subthreshold swing ~65 millivolts per decade and an On/Off current ratio ~10^6. This work provides new insight into the ultimate scaling of gate lengths for a FET by surpassing the 5 nm limit often associated with Si technology. Furthermore, the impact of using gate electrodes with limited density of states on the characteristics of nanoscale transistors is studied. Current work involves self- aligned doping of the extension regions in the device to improve On currents.


Current Active Projects:
BPN458
BPN862
BPN888
 

     Last Updated: Wed 2018-Feb-21 03:34:05

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